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MC10H179 Look-Ahead Carry Block
The MC10H179 is a functional/pinout duplication of the standard MECL 10K part, with 100% improvement in propagation delay and no increase in power supply current. * Power Dissipation, 300 mW Typical * Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) * Voltage Compensated * MECL 10K-Compatible
DIP PIN ASSIGNMENT
VCC1 GG CN+4 G0 G3 CN+2 G1 VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 PG P0 P3 P2 CN P1 G2 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week PLCC-20 FN SUFFIX CASE 775 PDIP-16 P SUFFIX CASE 648 1 1 10H179 AWLYYWW
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16 CDIP-16 L SUFFIX CASE 620 1 16 MC10H179P AWLYYWW MC10H179L AWLYYWW
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
ORDERING INFORMATION
Device MC10H179L MC10H179P MC10H179FN Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units/Rail 25 Units/Rail 46 Units/Rail
(c) Semiconductor Components Industries, LLC, 2000
June, 2006 - Rev. 7
1
Publication Order Number: MC10H179/D
MC10H179
MAXIMUM RATINGS
Symbol VEE VI Iout TA Tstg Power Supply (VCC = 0) Input Voltage (VCC = 0) Output Current- Continuous - Surge Operating Temperature Range Storage Temperature Range- Plastic - Ceramic Characteristic Rating -8.0 to 0 0 to VEE 50 100 0 to +75 -55 to +150 -55 to +165 Unit Vdc Vdc mA C C C
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V 5%) (See Note 1.)
0 Symbol IE IinH Characteristic Power Supply Current Input Current High Pins 5 and 9 Pins 4, 7 and 11 Pin 14 Pin 12 Pins 10 and 13 Input Current Low High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Propagation Delay P to PG G, P, Cn to Cn or GG Rise Time Min - - - - - - 0.5 -1.02 -1.95 -1.17 -1.95 Max 79 465 545 705 790 870 - -0.84 -1.63 -0.84 -1.48 Min - - - - - - 0.5 -0.98 -1.95 -1.13 -1.95 25 Max 72 275 320 415 465 510 - -0.81 -1.63 -0.81 -1.48 Min - - - - - - 0.3 -0.92 -1.95 -1.07 -1.95 75 Max 79 275 320 415 465 510 - -0.735 -1.60 -0.735 -1.45 Unit mA A
IinL VOH VOL VIH VIL tpd
A Vdc Vdc Vdc Vdc ns
AC PARAMETERS
0.4 0.6 0.5 1.4 2.3 1.7 0.4 0.7 0.5 1.5 2.4 1.8 0.5 0.8 0.5 1.7 2.6 1.9 ns
tr
tf Fall Time 0.5 1.7 0.5 1.8 0.5 1.9 ns 1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts.
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MC10H179
LOGIC DIAGRAM
G3 5 P3 13 G2 9 P2 12 2 GG 3 CN+4
CN 11 15 PG
G1 7 P1 10 G0 4 P0 14 PG = GG = CN + 2 = CN + 4 = P0 + P1 + P2 + P3 (G0 + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3 (CN + P0 + P1) (G0 + P1) G1 (CN + P0 + P1 + P2 + P3) (G0 + P1 + P2 + P3) (G1 + P2 + P3) (G2 + P3) G3 VCC1 VCC2 VEE = = = PIN 1 PIN 16 PIN 8
6 CN+2
TYPICAL APPLICATIONS The MC10H179 is a high-speed, low-power, standard MECL complex function that is designed to perform the look-ahead carry function. This device can be used with the MC10H181 4-bit ALU directly, or with the MC10H180 dual arithmetic unit in any computer, instrumentation or digital communication application requiring high speed arithmetic operation on long words. When used with the MC10H181, the MC10H179 performs a second order or higher look-ahead. Figure 2 shows a 16-bit look-ahead carry arithmetic unit. Second order carry is valuable for longer binary words. As an example, addition of two 32-bit words is improved from 30 nanoseconds with ripple-carry techniques. A block diagram of a 32-bit ALU is shown in Figure 1. The MC10H179 may also be used in many other applications. It can, for example, reduce system package count when used to generate functions of several variables.
FIGURE 1 - 32-BIT ALU WITH CARRY LOOK-AHEAD
Cin Cn P ALU Cn+4 G ALU Cn P G Cn P ALU Cn+4 G ALU Cn P G Cn P ALU Cn+4 G ALU Cn P G Cn P ALU Cn+4 G ALU Cn P G Add Time = 18 ns typ
Cn
Cn+2 MC10H179
Cn+4
Cn
Cn+2 MC10H179
Cn+4
Cout
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MC10H179
FIGURE 2 - 16-BIT FULL LOOK-AHEAD CARRY ARITHMETIC LOGIC UNIT
B1 A1 B0 A0 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 B12 A12 B13 A14 B14 A15 B15
A13
Cin 0
ABABABAB 00112233 Cn Cn + 4 M MC10H181 S0 G S1 4-BIT ARITHMETIC LOGIC UNIT S2 P S3 F0 F1 F2 F3
ABABABAB 00112233 Cn Cn + 4 M MC10H181 S0 G S1 4-BIT ARITHMETIC LOGIC UNIT S2 P S3 F0 F1 F2 F3
ABABABAB 00112233 Cn Cn + 4 M MC10H181 S0 G S1 4-BIT ARITHMETIC LOGIC UNIT S2 P S3 F0 F1 F2 F3
ABABABAB 00112233 Cn Cn + 4 M MC10H181 S0 G S1 4-BIT ARITHMETIC LOGIC UNIT S2 P S3 F0 F1 F2 F3
M S0 S1 S2 S3 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
P0 Cn
G0
P1
G1
P2
G2
P3
G3 G P
MC10H179 CARRY LOOK-AHEAD Cn + 4 Cn + 2 C15
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MC10H179
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D V A Z R 0.007 (0.180) M T L-M
S
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
Z
20
1
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
0.007 (0.180) M T L-M
S
N N
S
H K1 K
0.007 (0.180) M T L-M
S
N
S
S
C
E G G1 0.010 (0.250) S T L-M J 0.004 (0.100) -T- SEATING
PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180) M T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10H179
PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H K G D
16 PL
SEATING PLANE
J TA
M
M
0.25 (0.010)
M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10H179/D

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